Global planarization method using plasma etching
US5953578A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1998 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Sep 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer is planarized by first mapping the flatness profile and then etching the wafer according to the flatness profile. Mapping is accomplished by scanning the wafer with a light beam. The flatness information is obtained by a phase detector comparing the phase of the reflected light beam and a reference light, and is then stored in a memory. The etching is implemented with scanning chemical ion beam etching, in which a reactive gas etches the wafer from spot to spot according to the instantaneous volume of reacting gas or the potential at the wafer, and is controlled by the data stored in the memory. The method can be used to planarize both semiconductor and metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.