Computer memory system having programmable operational characteristics based on characteristics of a central processor
US5953740A · kind A · utility
5Cited by
13References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1993 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Oct 5, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.