Stack cache for stack-based processor and method thereof
US5953741A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Sep 14, 1999 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.