Synchronous memory device having an internal register
US5954804A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Feb 10, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is directed to an integrated circuit device having at least one memory section including a plurality of memory cells. The device includes an internal register to store an identification value which identifies the device on a bus. The device further includes interface circuitry, coupled to the bus, to receive identification information and a read request. The interface circuitry includes a plurality of output drivers and comparison circuitry. The output drivers are coupled to the bus to output data on the bus in response to the read request. The data is output synchronously with respect to first and second external clock signals when the comparison circuitry determines the identification information corresponds to the identification value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.