Data processing system and method for implementing a multi-port memory cell
US5956286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1997 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Oct 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The data processing system of the present invention implements a multi-port memory cell, wherein the port functions are divided based on a timing cycle in which they may be accessed. For example, in one case, a first port may be utilized only for read operations and accessed only during a first portion of the timing cycle. Similarly, a second port may be used for read or write operations and may be accessed only during a second portion of the timing cycle. To ensure that the multi-port memory cell functions correctly, both ports should not be accessed simultaneously. A circuit and method are implemented to ensure that both ports are not accessed simultaneously by implementing a delay function in a unique and useful manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.