Fault resilient/fault tolerant computing
US5956474A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Fault resilient or fault tolerant computers are produced by designating a first processor as a computing element, designating a second processor as a controller, connecting the computing element and the controller to produce a modular pair, and connecting at least two module pairs to produce a fault resilient or fault tolerant computer. Each computing element of the computer performs all instructions in the same number of cycles as the other computing element. The controllers provide input/output processings for the computing elements, as well as monitor their operations to detect errors, and control operation of the computing elements in response to the detected errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.