Bus arbiter including programmable request latency counters for varying arbitration priority
US5956493A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1996 |
| Grant date | Sep 21, 1999 |
| Priority date | — |
| Expiry date | Mar 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system is provided for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of counters referred to as "request latency" counters is further provided wherein a separate counter unit corresponds to each bus master. Each counter is configured to generate a signal indicative of a lapse of time since a time when the peripheral requested ownership of the bus. An arbitration control unit is coupled to the request latency counters, the request detection unit and the grant generator for processing incoming bus request signals. The arbitration control unit is configured to dynamically vary the level of arbitration priority given to each peripheral device based upon the latency signal corresponding to the device. Accordingly, as the time from when a peripheral device requests the bus increases, the level of arbitration priority given to that peripheral also increases. A set of programmable regis…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.