Method for producing SOI & non-SOI circuits on a single wafer

US5956597A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Toshiharu Furukawa · South Burlington, US
• Mark C. Hakey · Saint Albans, US
• Steven J. Holmes · Colchester, US
• David V. Horak · South Burlington, US
• Paul A. Rabidoux · Winooski, US

Key dates

• Filing date: Sep 15, 1997
• Grant date: Sep 21, 1999
• Expiry date: Sep 15, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.2 region is formed for the SOI devices, the expansion of the SOI region will bring the surface of the SOI device area up to the overall surface of the wafer. A short Chemical Mechanical …