Paul A. Rabidoux
38Patents
20h-index
21Co-inventors
77Inventor score
Filing activity: Sep 16, 1996 → May 26, 2004
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6096598A | Method for forming pillar memory cells and device formed thereby | Electricity | 156 | Expired |
| US6440801B1 | Structure for folded architecture pillar memory cell | Electricity | 118 | Expired |
| US6114725A | Structure for folded architecture pillar memory cell | Electricity | 86 | Expired |
| US6387783B1 | Methods of T-gate fabrication using a hybrid resist | Electricity | 77 | Expired |
| US6338934B1 | Hybrid resist based on photo acid/photo base blending | Emerging Cross-Sectional Technologies | 75 | Expired |
| US5945707A | DRAM cell with grooved transfer device | Electricity | 67 | Expired |
| US6114082A | Frequency doubling hybrid photoresist having negative and positive tone components and method of preparing the same | Physics | 49 | Expired |
| US6221562A | Resist image reversal by means of spun-on-glass | Physics | 48 | Expired |
| US6037194A | Method for making a DRAM cell with grooved transfer device | Electricity | 41 | Expired |
| US6303272A | Process for self-alignment of sub-critical contacts to wiring | Electricity | 36 | Expired |
| US6150256A | Method for forming self-aligned features | Electricity | 32 | Expired |
| US6007968A | Method for forming features using frequency doubling hybrid resist and device formed thereby | Physics | 32 | Expired |
| US6207514A | Method for forming borderless gate structures and apparatus formed thereby | Electricity | 31 | Expired |
| US7176089B2 | Vertical dual gate field effect transistor | Electricity | 28 | Expired |
| US6110653A | Acid sensitive ARC and method of use | Physics | 27 | Expired |
| US6200726A | Optimization of space width for hybrid photoresist | Emerging Cross-Sectional Technologies | 26 | Expired |
| US6194268A | Printing sublithographic images using a shadow mandrel and off-axis exposure | Emerging Cross-Sectional Technologies | 25 | Expired |
| US6531724B1 | Borderless gate structures | Electricity | 24 | Expired |
| US6184041A | Fused hybrid resist shapes as a means of modulating hybrid resist space width | Physics | 22 | Expired |
| US6319651A | Acid sensitive ARC and method of use | Physics | 20 | Expired |
| US5956597A | Method for producing SOI & non-SOI circuits on a single wafer | Electricity | 20 | Expired |
| US6313492A | Integrated circuit chip produced by using frequency doubling hybrid photoresist | Physics | 18 | Expired |
| US6014422A | Method for varying x-ray hybrid resist space dimensions | Emerging Cross-Sectional Technologies | 18 | Expired |
| US6284439A | "Method of producing an integrated circuit chip using low ""k"" factor hybrid photoresist and apparatus formed thereby" | Emerging Cross-Sectional Technologies | 18 | Expired |
| US6100172A | Method for forming a horizontal surface spacer and devices formed thereby | Electricity | 16 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.