System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver
US5958024A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Aug 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.