Electrically programmable memory cell arrangement and method for its manufacture

US5959328A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Wolfgang Krautschneider · Ottobrunn, DE
• Lothar Risch · Neubiberg, DE
• Franz Hofmann · Munich, DE
• Hans Reisinger · Grünwald, DE

Key dates

• Filing date: Jan 7, 1997
• Grant date: Sep 28, 1999
• Expiry date: Jan 7, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

An electrically programmable memory cell arrangement has a plurality of individual memory cells that respectively has an MOS transistor with a gate dielectric with traps, and which are arranged in rows that run in parallel. Adjacent rows thereby respectively run in alternating fashion on the bottom of the longitudinal trenches (5) and between adjacent longitudinal trenches (5) and are insulated against one another. The memory cell arrangement can be manufactured by means of self-adjusting process steps with a surface requirement per memory cell of 2 F.sup.2 (F: minimum structural size).