Phase-locked loop having improved locking times and a method of operation therefore
US5959478A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Oct 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic device is delineated comprising, in combination, a Phased Lock Loop (PLL) having a charge pump, and a mixed signal circuit coupled in parallel to the charge pump. The mixed signal circuit includes analog circuitry for adding charge to and removing charge from capacitors in a Low Pass Filer (LPF) of the PLL. The mixed signal circuit also includes digital circuitry for controlling the initiation and termination of both the charging and discharging operations carried on by the analog portion of the mixed signal circuit. Upon a significant change in system frequency, the mixed signal circuit first fully discharges and then rapidly charges the capacitors in the LPF in a manner which results in a significant reduction in PLL locking time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.