Memory controller with error correction memory test application
US5959914A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1998 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Mar 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/42
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and method for testing of memory locations containing both test data and test check bits are provided. The apparatus includes a memory controller that communicates with memory devices. In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data. The test data and test check bits are written to desired memory locations of the memory devices. The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations. The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read. Any lack of correspondence is indicative of one or more memory location faults. Both the test data and the test check bits are checked for accuracy during single transfer operations and the checking of the test check bits is conducted using at least some of the values of the associated test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.