Method of making EEPROM having coplanar on-insulator FET and control gate
US5960265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1997 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.