Flash EEPROM device

US5960285A · kind A · utility

Assignee

• United Semiconductor Corp. · TW

Inventor

• Gary Hong · Baoshan, TW

Key dates

• Filing date: Nov 21, 1997
• Grant date: Sep 28, 1999
• Expiry date: Nov 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0411

Abstract

A floating gate transistor is formed on an active device region defined between field isolation structures. A first polysilicon layer, or a layer of another conductor which can be used in diffusing impurities into the underlying silicon substrate, is provided on the active device region of the substrate and is covered by a layer of insulating material such as silicon oxide. The first polysilicon layer is doped by implantation of impurities, but no annealing step is performed at this time. An opening is formed through the polysilicon layer to expose the surface of the active device region. Oxide spacers and then nitride spacers are formed on the sidewalls of the opening in the first polysilicon layer to define a narrower opening. A gate oxide layer is grown on the active device region between the nitride spacers in a thermal oxidation process which preferably causes impurities to diffuse from the first polysilicon layer into the active device region on either side of the gate electrode, forming source/drain regions for the floating gate transistor. The nitride spacers are then removed in a wet etching process and then tunnel oxide layers are grown on the portions of the active devic…