Borderless contact etch process with sidewall spacer and selective isotropic etch process

US5960318A · kind A · utility

Assignees

• Siemens Aktiengesellschaft · DE
• International Business Machines Corporation · US

Inventors

• Matthias Peschke · Wien, AT
• Jeffrey P. Gambino · Gresham, US
• James G. Ryan · Sandy Hook, US
• Reinhard Stengl · Stadtbergen, DE

Key dates

• Filing date: Oct 27, 1995
• Grant date: Sep 28, 1999
• Expiry date: Oct 27, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76816
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of fabricating a self-aligned borderless contact in a semiconductor device. The semiconductor device includes a first conductor level, a patterned conductor level defining a pair of spaced apart conducting segments, and a dielectric insulating layer disposed between the first conductor level and the patterned conductor level, and over the pair of spaced apart conducting segments of the patterned conductor level. The method comprises the steps of etching a contact hole in a selected region of the dielectric insulating layer which lies above and is substantially aligned between the pair of the segments. The etching continues through the dielectric insulating layer so that a portion of the dielectric insulating layer remains between the contact hole and the first conductor level. A spacer is formed which lines the contact hole. The remaining portion of the insulating layer which extends between the contact hole and the first conductor level is then etched to extend the contact hole to the first conductor level. The spacer substantially prevents the erosion of the pair of spaced apart segments during the etching of the remaining portion of the insulating layer. The contact hol…