Memory controller having precharge prediction based on processor and PCI bus cycles
US5960459A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1998 |
| Grant date | Sep 28, 1999 |
| Priority date | — |
| Expiry date | Aug 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and seve…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.