Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency
US5961630A · kind A · utility
40Cited by
4References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Dec 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3858
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second instruction that follows the first instruction; and scheduling for execution the first instruction and the second instruction separated from the first instruction by an amount of time at least equal to the post-ready latency of the second instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.