Single transistor ferroelectric memory cell with asymmetrical ferroelectric polarization and method of making the same
US5962884A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Aug 4, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Aug 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate includes implanting doping impurities of a first type into the substrate to form a conductive channel of a first type, implanting doping impurities of a second type in the conductive channel of the first type to form a conductive channel well of a second type, implanting doping impurities of a third type in the conductive channel well of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type in the conductive channel sub-well of the third type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region. A ferroelectric memory cell includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.