Address translation unit employing programmable page size
US5963984A · kind A · utility
68Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1997 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for virtual addressing are disclosed having an address translation unit with variable page size by employing direct, victim, and programmable block translation look aside buffers. Selective comparisons between contents on a linear address bus and linear address tags are controlled by a size mask register which further controls a multiplexer to selectively steer bits onto a physical address bus from either the linear address bus or a physical address register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.