Integrated circuit layout methods and layout structures
US5965925A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 1997 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Oct 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor layout design for use in integrated circuits that use balance circuitry. The semiconductor layout design includes a set of four substantially self enclosing gate transistors being arranged symmetrically about a common point. Wherein, each of the set of four substantially self enclosing gate transistors have a gate width that is defined by a perimeter around each of the set of four substantially self enclosing gate transistors. The semiconductor layout design preferably includes a balanced circuit having a set of first transistors and a set of second transistors. The set of first transistors being wired diagonally across the set of four substantially self enclosing gate transistors. In a preferred embodiment, the set of second transistors are wired diagonally across the set of four substantially self enclosing gate transistors in a manner that ensures that the set of second transistors are wired substantially perpendicular to the set of first transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.