Method of manufacturing an integrated circuit using chemical mechanical polishing
US5967885A · kind A · utility
12Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B37/042
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
A method of manufacturing integrated circuits using a carrier fixture. The carrier fixture does not include transport channels or openings for directing a slurry to a substrate being polished and, as a result, damage to the substrate is reduced because the edges adjacent to the substrate are eliminated. The present invention further provides a carrier fixture having an inner support coupled to a ring member that contacts a substrate during the CMP process. The present invention also provides a carrier fixture having inner and outer supports coupled to a ring member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.