Method and apparatus for testing integrated circuits in a mixed-signal environment
US5968191A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Apr 28, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Apr 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/66
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus is disclosed for testing integrated circuit interconnect and measuring the value of passive component interconnecting the IC's. Each IC includes both analog and digital circuitry and is provided with a test access port and boundary scan architecture for selectively connecting components to an analog test bus and for testing for the integrity of interconnections. When connected with the test bus, a constant current is supplied to the component and the resulting voltage developed across the bus is used for identifying the value of the component. In a second embodiment each IC includes a pair of buses which permits measurement of the impedance of the switches connecting the components to the test bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.