Programmable universal test interface and method for making the same
US5968192A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | May 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a programmable memory test interface. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.