Power source design for embedded memory
US5970011A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1998 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Nov 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.