Method of fabricating a microelectronic package having polymer ESD protection
US5970321A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.