Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer
US5970376A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 1997 |
| Grant date | Oct 19, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/963
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a low dielectric constant dielectric layer, where the low dielectric constant dielectric layer is formed from a silsesquioxane spin-on-glass (SOG) dielectric material. There is then formed over the low dielectric constant dielectric layer a patterned photoresist layer. There is then etched through use of a fluorine containing plasma etch method while employing the patterned photoresist layer as a photoresist etch mask layer the low dielectric constant dielectric layer to form a patterned low dielectric constant dielectric layer having a via formed therethrough. The fluorine containing plasma etch method employing a fluorine containing etchant gas composition which simultaneously forms a fluorocarbon polymer residue layer upon a sidewall of the via. There is then treated through use of a plasma treatment method the fluorocarbon polymer residue layer to form a plasma treated fluorocarbon polymer residue layer. The plasma treated fluorocarbon polymer residue layer is susc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.