Inventor · Hsinchu, TW

Chao-Cheng Chen

214Patents
21h-index
206Co-inventors
93Inventor score

Filing activity: Mar 20, 1997 → Jun 4, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US6277752A Multiple etch method for forming residue free patterned hard mask layer Electricity 267 Expired
US6440863B1 Plasma etch method for forming patterned oxygen containing plasma etchable layer Electricity 235 Expired
US6323121A Fully dry post-via-etch cleaning method for a damascene process Electricity 109 Expired
US5970376A Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer Emerging Cross-Sectional Technologies 77 Expired
US6025273A Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask Electricity 61 Expired
US6040248A Chemistry for etching organic low-k materials Electricity 49 Expired
US6211061A Dual damascene process for carbon-based low-K materials Electricity 48 Expired
US5981398A Hard mask method for forming chlorine containing plasma etched layer Electricity 47 Expired
US5807789A Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) Emerging Cross-Sectional Technologies 44 Expired
US5942446A Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer Electricity 42 Expired
US8507979B1 Semiconductor integrated circuit with metal gate Electricity 36 Active
US6444517B1 High Q inductor with Cu damascene via/trench etching simultaneous module Electricity 34 Expired
US6194128A Method of dual damascene etching Electricity 31 Expired
US9214358B1 Equal gate height control method for semiconductor device with different pattern densites Electricity 30 Active
US9536980B1 Gate spacers and methods of forming same Electricity 27 Active
US6027861A VLSIC patterning process Electricity 25 Expired
US9431304B2 Method and structure for metal gates Electricity 24 Active
US9761684B2 Method and structure for metal gates Electricity 24 Active
US9245883B1 Method of making a FinFET device Electricity 23 Active
US8748989B2 Fin field effect transistors Electricity 22 Active
US6319822A Process for forming an integrated contact or via Electricity 22 Expired
US6790770B2 Method for preventing photoresist poisoning Electricity 21 Expired
US7759239B1 Method of reducing a critical dimension of a semiconductor device Electricity 20 Active
US6309962A Film stack and etching sequence for dual damascene Electricity 17 Expired
US6429119B1 Dual damascene process to reduce etch barrier thickness Electricity 17 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.