Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile

US5972752A · kind A · utility

Assignee

• United Semiconductor Corp. · TW

Inventor

• Gary Hong · Baoshan, TW

Key dates

• Filing date: Dec 29, 1997
• Grant date: Oct 26, 1999
• Expiry date: Dec 29, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A method for forming a flash memory cell structure comprising the steps of providing a semiconductor substrate, and then sequentially forming a bottom conductive layer and a cap oxide layer over the substrate. Next, a pattern is defined in the conductive layer and the cap oxide layer. Subsequently, a thermal oxidation method is used to form a silicon oxide layer on the sidewalls of the bottom conductive layer. Then, a gate oxide layer is formed between the bottom conductive layers above the substrate. Thereafter, source/drain regions are formed in the semiconductor substrate. Then, spacer structures are formed adjacent to the silicon oxide layers. Using the spacer structures as masks, a portion of the gate oxide layer is etched. Then, the spacer structures are removed to expose the gate oxide layer. Next, a thermal oxidation method is used to form a tunneling oxide layer in the narrow region between the gate oxide layer. The tunneling oxide layer has a long narrow top profile. Finally, a floating gate layer, a dielectric layer and a control gate are sequentially formed to complete the flash memory cell structure.