Method for fabricating MOSFET having increased effective gate length
US5972754A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated by field oxide regions; forming a lightly doped region in each active area; forming a heavily doped p-Si (or a-Si) layer; depositing and patterning several dielectric layers to form a gate area surrounded by vertical spacers; forming a groove in the gate area and the substrate; forming a gate oxide layer in the groove and driving dopants in the doped p-Si (or a-Si) layer into the substrate to form the source and the drain; and forming a gate electrode in the groove.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.