Prevention of die loss to chemical mechanical polishing
US5972798A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modem high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.