DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness
US5973361A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new transistor cell is disclosed in this invention which is formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of the substrate. The DMOS cell includes a polysilicon layer constituting a gate supported on a top surface of the substrate, the gate surrounding and defining an outer boundary of the transistor cell having a removed polysilicon opening disposed substantially in a central portion of the cell. The DMOS cell further includes a source region of the first conductivity disposed in the substrate near edges of the removed polysilicon opening with a portion extends underneath the gate. The DMOS cell further includes a body region of a second conductivity type disposed in the substrate occupying an entire region under the removed polysilicon opening thus encompassing the source region and having a portion extends underneath the gate. The body region defining substantially a merged-double-U-shaped region including a left-U-shaped implant region and a right-U-shaped implant region and a merged region disposed substantially at a central portion under the removed polysilicon opening. In a preferred embodiment, the merged d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.