CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator
US5973363A · kind A · utility
116Cited by
34References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1995 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Mar 9, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising an insulating substrate; a layer of silicon formed on said insulating substrate; a p-channel transistor and an n-channel transistor formed in said silicon layer and interconnected in a CMOS circuit; wherein the ratio of transistor p-channel length to transistor n-channel length in the CMOS circuit is less than or equal to one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.