MOS transistor and lateral insulating method of a MOS transistor active region
US5973365A · kind A · utility
5Cited by
3References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS type field effect transistor including a portion of silicon layer (114) forming an active region (114a) placed between a grid oxide layer (120) and a buried oxide layer (112), and laterally delimited by lateral oxide insulation blocks (116). The portion of the silicon layer (114) has concave edges (122, 124) facing the lateral oxide insulation blocks (116). The transistor is applicable to the manufacture of integrated circuits with low electricity consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.