Semiconductor device with marginless contact hole
US5973371A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Jul 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A semiconductor device is provided, which is capable of miniaturization to a level corresponding to 1-Gb DRAMs. A first interlayer insulating layer is formed on or over a semiconductor substrate to cover a first-level conductive layer. First and second conductive sublayers of a second-level conductive layer are formed on the first interlayer insulating layer. First and second insulating caps are formed on the first and second sublayers, respectively. A lower contact hole penetrating the first insulating layer is formed to be self-aligned with the first and second sublayers. A conductive pad is formed on the first-level conductive layer in the lower contact hole to be electrically insulated from the first and second sublayers by an insulating spacer. A second interlayer insulating layer with an upper contact hole communicating with the lower contact hole is formed on the first interlayer insulating layer. A third-level conductive layer is formed on the second interlayer insulating layer to be contacted with the conductive pad through the upper contact hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.