Flash memory array having well contact structures
US5973374A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Sep 25, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Sep 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A common source flash memory array providing multiple well contact structures distributed within the array without the need for separate well tap regions connected to dedicated channel lines. The contact locations between Vss metal common source lines and source bus regions are used to provide additional contacts between Vss metal lines and p+ well taps, all of the source bus regions and the p+ well tap regions being encompassed within a double-well configuration. Depending on the specific embodiment of the present invention, the n+ diffused source bus regions and the nearby p+ well tap may: (a) be separately tied to the Vss metal common source line through separate contact metals (e.g., tungsten plugs); (b) be butted against each other and tied to a common Vss metal source line through separate contact metals; (c) be butted against each other and tied to a common Vss metal source line through a common contact metal (e.g., an enlarged plug) overlapping both the n+ diffused source bus regions and the p+ well tap; or (d) be tied to a common Vss metal source line through a common contact metal and a metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.