Phase lock loop circuit with variable loop gain
US5973572A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Mar 12, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL (phase lock loop) circuit improves pull-in and noise performances by changing a loop gain based on the loop states. The PLL circuit includes a voltage controlled oscillator (VCO) for generating an oscillation signal whose oscillation frequency is controlled by a control voltage provided thereto, a phase comparator for detecting a phase difference between the oscillation signal from the VCO and a reference signal wherein a detection gain of the phase difference is regulated by a bias voltage provided thereto, a low pass filter for receiving an output signal of the phase comparator for removing high frequency components therefrom to produce the control voltage supplied to the VCO, a phase lock loop formed by the VCO, phase comparator and low pass filter, and a phase lock detection circuit for detecting whether the phase lock loop has reached a phase lock state and changing the bias voltage to decrease the detection gain of the phase comparator when the phase lock loop has reached the lock state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.