Circuit and method of reading cells of an analog memory array, in particular of the flash type
US5973959A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Jul 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reading circuit comprises a current mirror circuit connected, at a first and a second output node, to the drain terminals of an array cell and of a reference cell; a comparator whose inputs are connected to the output nodes of the current mirror circuit; a ramp generator having an enabling input connected to the output of the comparator and an output connected to the control terminal of the reference cell. Biasing the gate terminal of the array cell to a constant voltage, when the currents flowing in the array cell and in the reference cell are equal, the value assumed by the ramp voltage is proportional to the threshold value of the array cell; at that time the comparator is triggered and discontinues the ramp increase, supplying as output the desired threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.