Page buffer having negative voltage level shifter
US5973967A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell. When the data signal is in a second logic state, the cross-coupled latch turns off the pass transistor and allows the bit line to float which, in turn, precludes programming of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.