Computer system having distributed compression and decompression logic for compressed data movement
US5974471A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A computer system having distributed compression and decompression logic for compressed data movement within the computer system. This provides increased efficiency and reduced bus bandwidth requirements. The computer system includes various standard components, including a CPU, chip set logic, main memory, one or more expansion buses, and various peripheral devices coupled to the expansion buses. Various devices may be connected to the PCI bus, including graphics accelerator hardware, audio logic, a hard drive, and a network interface card, and other multimedia devices, as desired. In the preferred embodiment, the bridge logic and/or memory controller, one or more of the multimedia devices, the hard drive, and the network interface controller each includes compression/decompression (codec) logic which performs compression and decompression operations. Thus, when a device desires to perform a transfer on the bus, the codec in the device preferably compresses the data before transferring the data onto the bus. The receiving or destination device includes codec logic which receives the compressed data and decompresses the data, and the decompressed data is then used or stored by the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.