Using a back-off signal to bridge a first bus to a second bus
US5974495A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1998 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | May 29, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/7219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PCI-bus is added to a VESA local bus (VL-bus) computer system using a VL-bus/PCI-bus bridge. The VL-bus/PCI-bus bridge claims a VL-bus cycle by asserting LDEV# to the VL-bus/system-bus bridge. If no other VL-bus device claims the cycle as well, then the VL-bus/PCI-bus bridge translates the cycle onto the PCI-bus and awaits a response from a PCI device. If no PCI device claims a cycle by the PCI-bus device claiming deadline, then the VL-bus/PCI-bus bridge asserts BOFF# to the host and suppresses its assertion of LDEV# when the host repeats the cycle on the VL-bus. The VL-bus/system-bus bridge therefore can translate the repetition of the cycle onto the system bus. When asserting BOFF# to the host, the VL-bus/PCI-bus bridge also asserts the VL-bus device ready signal LRDY# after assertion of BOFF# and releases LRDY# before releasing BOFF#. The VL-bus controller does not receive BOFF# necessarily, but responds to LRDY# by asserting RDYRTN# onto the VL-bus, thereby signifying to all other VL-bus devices that the VL-bus cycle has ended and permitting them to restart their state machines in anticipation of a new VL-bus cycle. The host ignores RDYRTN# while, and only while, BOFF# is ass…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.