Method and apparatus for detecting memory device types
US5974501A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1996 |
| Grant date | Oct 26, 1999 |
| Priority date | — |
| Expiry date | Dec 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller and method of operation for detecting different type of dynamic random access memory (DRAM) devices in a computer system. The memory controller has capabilities for improved page hits which cause the row address strobe signals to remain asserted following certain cycles. A mechanism in the memory controller selectably disables column address strobing. Different DRAM types are distinguishable by reading back data previously written to a memory location. Data is written to memory with a cycle causing the memory controller to keep the row address strobes asserted. Column address strobing is disabled. A read back cycle is performed without column address strobing. If data is present, the DRAM is an extended data output (EDO) DRAM. If data is not present, the DRAM is a fast page mode DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.