Semiconductor memory device including memory cells having a capacitor on bit line structure
US5977583A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
In a method of fabricating a COB DRAM cell, a polysilicon plug is formed on the source and drain in self-alignment with the gate electrode. A bit line contact and a storage electrode contact are formed on the polysilicon plug thereby to reduce the aspect ratio of both the bit line contact and the storage electrode contact. With the polysilicon plug formed in self-alignment with the gate electrode, short-circuiting of contacts of adjacent element regions and short-circuiting of the plugs of the source and drain will not occur, leading to high protection against misregistration. Moreover, an independent lithography process is not required for forming the polysilicon plug, and, therefore, the number of fabrication steps is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.