Diffusion barrier for electrical interconnects in an integrated circuit
US5977634A · kind A · utility
3Cited by
11References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical interconnect structure comprising a diffusion barrier and a method of forming the structure over a semiconductor substrate. A bi-layer diffusion barrier is formed over the substrate. The barrier comprises a capturing layer beneath a blocking layer. The blocking layer is both thicker than the capturing layer and is unreactive with the capturing layer. A conductive layer, thicker than the blocking layer, is then formed over the barrier. While the conductive layer is unreactive with the blocking layer of the barrier, the conductive layer is reactive with the capturing layer of the barrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.