Logic array having interleaved logic planes
US5977794A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic array includes a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The third logic plane has first and second opposing sides and is adapted to receive the first and second pluralities of intermediate outputs. The first plurality of intermediate outputs intersect the third logic plane through the first side, and the second plurality of intermediate outputs intersect the third logic plane through the second side. A method for increasing the density of a logic array includes providing a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The first plurality of intermediate outputs and the second plurality of intermediate outputs are interleaved in the third logic plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.