Erase and program control state machines for flash memory
US5978275A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Aug 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase state machine controls the process of erasing all the memory cells in a selected sector of a flash memory array. The erase state machine includes a sequence of states for controlling generation of high positive and negative voltages, and application of the high positive voltage to all word lines in the selected sector and application of the high negative voltage to the source nodes of all memory cells in the selected sector. A sequence of two discharge states are used to discharge the high voltages from the word lines and source nodes. If an erase operation is aborted while high voltages are being generated, the erase state machine asynchronously transitions to the first of the two discharge states, and then transitions to the second discharge state and then back to a final inactive state during successive state machine clock cycles. Further, the erase state machine simultaneously checks all the cells in the selected sector to see if they are fully erased, without having to use a repeating loop of states for that purpose. The program state machine controls the programming of one page of flash memory cells. It enables the use of N/2.sup.k programming bit latches in the memo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.