Method and apparatus for preventing postamble corruption within a memory system
US5978281A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1999 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Jan 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A postamble corruption protection circuit is provided that disables data latching by a first falling edge register following a data strobe (DQS) falling edge until the data within the first falling edge register has been latched into a second falling edge register in response to a second falling edge register latching signal. Specifically, data latching by the first falling edge register is disabled following each DQS falling edge and is enabled following each second falling edge register latching signal. Data latching of the first falling edge register is controlled by the output of a set/reset register which is gated with the DQS to form a first falling edge register latching signal. When the set/reset register is set, data latching is enabled and when the set/reset register is reset, data latching is disabled. The set/reset register is set in response to a second falling edge register latching signal and is reset in response to a DQS falling edge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.