Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combination with the internal clock to control transmission of data words to an external memory
US5978926A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1998 |
| Grant date | Nov 2, 1999 |
| Priority date | — |
| Expiry date | Mar 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.