MIPS Technologies, Inc.
🏢 View company profile →272Patents
135Active
272Granted
49Portfolio score
Filing activity: May 17, 1993 → Mar 7, 2013 · 128 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5933650A | Alignment and ordering of vector elements for single instruction multiple data processing | Physics | 204 | Expired |
| US5864703A | Method for providing extended precision in SIMD vector arithmetic operations | Physics | 116 | Expired |
| US5450607A | Unified floating point and integer datapath for a RISC processor | Physics | 101 | Expired |
| US7055070B1 | Trace control block implementation and method | Physics | 101 | Expired |
| US6266758A | Alignment and ordering of vector elements for single instruction multiple data processing | Physics | 100 | Expired |
| US7020879B1 | Interrupt and exception handling for multi-streaming digital processors | Physics | 97 | Expired |
| US6216200A | Address queue | Physics | 96 | Expired |
| US7181484B2 | Extended-precision accumulation of multiplier output | Physics | 83 | Expired |
| US7177985B1 | Microprocessor with improved data stream prefetching | Physics | 81 | Expired |
| US6594728B1 | Cache memory with dual-way arrays and multiplexed parallel output | Physics | 79 | Expired |
| US7185183B1 | Atomic update of CPO state | Physics | 77 | Expired |
| US6754804B1 | Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions | Physics | 69 | Expired |
| US7185234B1 | Trace control from hardware and software | Physics | 66 | Expired |
| US7321965B2 | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor | Physics | 65 | Expired |
| US7257814B1 | Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors | Physics | 62 | Expired |
| US7634638B1 | Instruction encoding for system register bit set and clear | Physics | 59 | Expired |
| US7242414B1 | Processor having a compare extension of an instruction set architecture | Physics | 58 | Expired |
| US6742165B2 | System, method and computer program product for web-based integrated circuit design | Physics | 58 | Expired |
| US6681283B1 | Coherent data apparatus for an on-chip split transaction system bus | Physics | 53 | Expired |
| US6789100B2 | Interstream control and communications for multi-streaming digital processors | Physics | 51 | Expired |
| US6393500B1 | Burst-configurable data bus | Physics | 51 | Expired |
| US6493776B1 | Scalable on-chip system bus | Physics | 50 | Expired |
| US7376954B2 | Mechanisms for assuring quality of service for programs executing on a multithreaded processor | Physics | 47 | Expired |
| US8145882B1 | Apparatus and method for processing template based user defined instructions | Physics | 46 | Active |
| US7181600B1 | Read-only access to CPO registers | Physics | 46 | Expired |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.