Method for maximizing interconnection integrity and reliability between integrated circuits and external connections
US5981370A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1997 |
| Grant date | Nov 9, 1999 |
| Priority date | — |
| Expiry date | Dec 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device which includes providing a shaped bond pad, preferably rectangular or oval. A cavity followed by a hill are formed in the bond pad by performing a probe test at one end portion of the bond pad. Then a ball bond is formed on the bond pad remote and spaced from the cavity. The ball bond can extend onto the hill or be spaced from the hill. The bond pad preferably has a greater length than width and the cavity, hill and ball bond are disposed successively along the length of the bond pad. The length of the bond pad in the direction normal to the cavity, the hill and the ball bond is greater than the sum of the diameter of a probe tip with which a probe test will be made on the bond pad and the diameter of the ball bond.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.